Electrical modeling of through-silicon-via for 3D integrated circuits

117 p.Increased use of technology in day to day life for seamless activity and increased living comforts have been driving the Integrated Circuit (IC) industry to produce better hardware at cheaper and faster rate. Hence Ultra Large Scale Integration (ULSI) of ICs is accelerating to account for the need of high speed systems. Traditional scaling alone is believed to be insufficient to satisfy the interconnect performance going forward. Hence equivalent scaling using unconventional approaches would be necessary. As the scaling of integrated circuits to achieve faster, denser and smaller devices continues to drive the industry, we are at the juncture where many hurdles need to be addressed to continue on this remarkable journey of semiconductors. International Technology Roadmap for Semiconductors [ITRS] projects that the device delay is continuously scaling down but interconnect delays are increasing at a rapid rate for global and semi global interconnectsMaster of Science (Electronics

Compact modeling and circuit design of resistive memory devices for innovative applications

Les limites rencontrées par les dernières générations de mémoires Flash et DRAM (Dynamic Random Access Memory) nécessitent la recherche de nouvelles variables physiques (autres que la charge et la tension), de nouveaux dispositifs ainsi que de nouvelles architectures de circuits. Plusieurs dispositifs à résistance variable sont très prometteurs. Parmi eux, les OxRRAMs (Oxide Resistive Random Access Memory) et les CBRAMs (Conductive Bridge Random Access Memory) sont de sérieux candidats pour la prochaine génération de mémoire dense. Ce travail se concentre donc sur le rôle des mémoires résistives (OxRRAM et CBRAM) dans les mémoires embarquées et plus particulièrement dans les FPGAs. Pour cela, nous avons développé un modèle compact, outil indispensable à la conception de circuits intégrés. Ensuite, nous avons conçus de nouveaux circuits non volatiles tels que des flips-flops (NVFF), des tables de correspondance (NVLUT), des commutateurs 2x2 ainsi que des SRAMs (NVSRAM). Ces structures ont finalement été simulées dans le cas d’un FPGA, afin de vérifier l’impact de celles-ci sur la surface, le délai ainsi que la puissance. Nous avons comparé les résultats pour un FPGA à base de NVLUTs utilisant une structure 1T-2R composée de CBRAMs par rapport à un FPGA plus classique utilisant des SRAMs. Nous réduisons ainsi la taille de 5%, la consommation de 18% et améliorons la vitesse de fonctionnement de 24%. La thèse aborde la modélisation compacte, la conception des circuits, et l’évaluation de systèmes incluant des mémoires résistives.The grave challenges to future of traditional memories (flash and DRAM) at 1X nm regime has resulted in increased quest for new physical state variables (other than charge or voltage), new devices and architectures offering memory and logic functions beyond traditional transistors. Many thin film devices with resistance change phenomena have been extensively reported as ’promising candidates’. Among them, Ox- ide Resistive Memory (OxRRAM) and Conductive Bridge Resistive Memory (CBRAM) are leading contenders for the next generation high density memories. In this work, we focus on the role of Resistive Memories in embedded memories and their impact on FPGAs in particular. We begin with the discussion on the compact modeling of resistive memory devices for design enabling, we have designed novel circuits of non- volatile flip-flop (NVFF), non-volatile look-up table (NVLUT), non-volatile 2x2 switch and non-volatile SRAM (NVSRAM) using Resistive Memories. We simulated the impact of these design structures on the FPGA system assessing the performance parameters of area, delay and power. By using the novel 1T-2R memory element concept of CBRAMs in FPGAs to implement Look-up Tables (NVLUT), we would scale down the area impact by 5%, enhance speed by 24% and reduce the power by 18% compared to SRAM based FPGAs. The thesis addresses aspects of compact modeling, circuit design and system evaluation using resistive memories

Oxide based resistive RAM: ON/OFF resistance analysis versus circuit variability

International audienceA deeper understanding of the impact of variability on Oxide-based Resistive Random Access Memory (so-called OxRRAM) is needed to propose variability tolerant designs to ensure the robustness of the technology. Although research has taken steps to resolve this issue, variability remains an important characteristic for OxRRAMs. In this paper, impact of variability on OxRRAM circuit performances is analysed quantitatively at a circuit level through electrical simulations. Variability is introduced at the memory cell level but also at the peripheral circuitry level. The aim of this study is to determine the contribution of each component of an OxRRAM circuit on the ON/OFF resistance ratio

RRAM-based FPGA for “Normally Off, Instantly On” applications

International audience“Normally Off, Instantly On” applications are becoming common in our environment. They range from healthcare to video surveillance. As the number of applications and their associated performance requirements grow rapidly, more and more powerful, flexible, and power efficient computing units are necessary. In such a context, Field Programmable Gate Arrays (FPGA) architectures present a good trade-off between performance and flexibility. However, they consume high static power and can hardly be associated with power-gating techniques due to their long context-restoring phase. In this paper, we propose to integrate non-volatile resistive memories in the configuration cells and registers in order to instantly restore the FPGA context. If the circuit is in the ‘ON’ state for less than 42% of time, non-volatile FPGA starts saving energy compared to classical FPGA. Finally, when context-saving functionality is included, for a typical application with only 1% of time spent in the ‘ON’ state, the energy gain exceeds 40

Bipolar ReRAM Based Non-­‐Volatile Flip-­‐flops for Low-­‐Power Architectures

International audience—Resistive Random Access Memories (ReRAMs) fabricated in the back-end-of-line are a promising breakthrough for including permanent retention mechanisms in embedded systems. This low-cost solution opens the way to advanced power management schemes. In this paper, we propose novel design architecture of a non-volatile flip-flop based on Bipolar ReRAMs (Bi-RNVFF). Compared to state-of-the-art Data-Retention flip-flop (with Balloon latch), the proposed design is 25% smaller due to 6T structure compared to the 8T structure of Data-Retention flip-flop. Moreover, being non-volatile, the proposed architecture exhibits a zero leakage compared to a Data-Retention Flip-Flop, which consumes ~3.2µW in sleep mode (leakage) for a 10K Flip-Flop design implemented in 22nm FDSOI technology. Our simulation results show that Bi-RNVFF is a true alternative for future " Power-on, Power-off " application adding Non-Volatility without significant burdening of the existing architectures

Resistive memories: Which applications?

International audienc

Compact Modeling Solutions for Oxide-Based Resistive Switching Memories (OxRAM)

International audienceEmerging non-volatile memories based on resistive switching mechanisms attract intense R&D efforts from both academia and industry. Oxide-based Resistive Random Acces Memories (OxRAM) gather noteworthy performances, such as fast write/read speed, low power and high endurance outperforming therefore conventional Flash memories. To fully explore new design concepts such as distributed memory in logic, OxRAM compact models have to be developed and implemented into electrical simulators to assess performances at a circuit level. In this paper, we present compact models of the bipolar OxRAM memory based on physical phenomenons. This model was implemented in electrical simulators for single device up to circuit level. J. Low Power Electron. Appl. 2014, 4

Design and Simulation of a 128 kb Embedded Nonvolatile Memory Based on a Hybrid RRAM (HfO2_2 )/28 nm FDSOI CMOS Technology

International audienceEmerging nonvolatile memories (NVM) based on resistive switching mechanism such as RRAM are under intense R&D investigation by both academics and industries. They provide high write/read speed, low power, and good endurance (e.g., >10$^{12}$) beyond mainstream NVMs, enabling them to be a good candidate for Flash replacement in microcontroller unit. This replacement could significantly decrease the power consumption and the integration cost on advanced CMOS nodes. This paper presents first the HfO$_2$-based RRAM technology and the associated compact model, which includes related physics and model card fitting experimental electrical characterizations. The 128 kb memory architecture based on RRAM technology and 28 nm fully depleted silicon on insulator (FDSOI) CMOS core process is presented with a bottom-up approach, starting from the bit-cell definition up to the complete memory architecture implementation. The key points of the architecture are the use of standard logic MOS exclusively, avoiding any high voltage MOS usage, program/verify procedure to mitigate cycle to cycle variability issue and direct bit-cell read access for characterization purpose. The proposed architecture is validated using postlayout simulations on MOS and RRAM corner cases

Operation and stability analysis of bipolar OxRRAM-based Non-Volatile 8T2R SRAM as solution for information back-up

International audienceThis work presents a Non-Volatile SRAM (NV-SRAM) cell, resilient to information loss. The cell features fast storage (20ns) for the operating voltage of 1.0V. The information is backed-up during POWER-DOWN/ RECOVERY cycle in two bipolar Oxide Resistive RAMs (OxRRAMs). The proposed NV-SRAM is designed with an 8T2R structure using 22nm FDSOI technology and resistive memory devices based on HfO 2. The stability and the reliability of the NV-SRAM cell is investigated by taking into account the variability of the transistors. It is shown that high R OFF /R ON is necessary to ensure reliable RECOVERY operation and high SRAM yield under cell area and power consumption constraints